Signal path:

a. Block Diagram Analysis

Signals in the range of 15 KHz to 29.9999 MHz enter the Preselector from the antenna input, and pass through an overload protector circuit. The operator can select whether the signal passes through a single RF circuit tuned to the desired frequency, or it can (in the WIDEBAND position) bypass the tuned circuit. The signal then passes through a 40 MHz low-pass filter at the Preselector output.

From the Preselector, the signal is fed through a bandpass RF amplifier to the First Mixer, where it is up-converted by the operator-selected synthesizer output. The output of the First Mixer is fed to the 92 MHz First IF Amplifier. The output of the First Mixer is passed through a 20 KHz wide 4-pole crystal bandpass filter centered on 92 MHz, and then to the 92 MHz IF amplifier, where it is amplified and passed through another bandpass filter. Delayed AGC voltage is applied to this dual gate FET IF amplifier. The output of the second 92 MHz filter goes into the diode quad Second Mixer, where it is mixed with the 84 MHz second injection signal to produce an 8 MHz second IF signal.

The 8 MHz second IF signal leaves the Second Mixer through an 8 KHz wide crystal bandpass filter. This filter is the narrowest filter in the signal path when the 8 KHz bandwidth is selected by the operator.

The output of the 8 KHz wide crystal filter is amplified by an 8 MHz IF amplifier, to which IF AGC voltage is applied. The output of the amplifier is routed through an operator-selected Information Filter (2 KHz, 3 KHz, 400 Hz, USB, or LSB) and then to a second 8 MHz IF amplifier.

The output of the second 8 MHz IF amplifier is applied to three different detector chains:
  • AM detector chain,
  • Product detector chain, and
  • AGC chain.

The AM chain consists of an 8 MHz preamplifier and a voltage doubler diode AM detector. These circuits are enabled only when AM operation is selected.

The product detector chain consists of an 8 MHz amplifier/buffer that feeds the product detector. This chain is enabled for all modes except AM.

The audio outputs from both the AM chain and the Product Detector chain are fed through isolating resistors to a common line feeding the audio preamplifier; output from the audio preamplifier feeds the audio power amplifier.

The AGC chain consists of an 8 MHz AGC amplifier, a full wave diode AGC detector, DC amplifiers, and AGC delay circuitry.

b. Preselector

The preselector consists of four parts: input overload protection circuit, tunable RF circuits, a 40 MHz low-pass filter, and a switchable (20 dB) attenuator.

The input overload protection circuit is a diode pair that symetrically clips on peaks greater than approximately 3 volts. This clipper prevents the destruction of the RF amplifier by energy from nearby transmitters.

A low-pass filter is provided for the 15 KHz to 100 KHz range. THe RF coils tune in 8 ranges from 100 KHz to 30 MHz by means of a variable capacitor adjusted from the front panel. Below 4 MHz the tuned circuits are top-capacity-input coupled to provide a high impedance input for the type of antenna normally encountered in this frequency range. Above 4 MHz the tuned circuits are designed for 50 Ohm antennas.

The 40 MHz low-pass filter provides attenuation for input signals above the 30 MHz top frequency limit of the receiver. A parallel-tuned trap at 92 MHz attenuates energy at that frequency that otherwise might be able to feed into the first IF amplifier of the receiver.

A relay-controlled 20 dB attenuator, switched in at the receiver front panel, minimizes desensitization and cross modulation caused by strong off-channel undesired signals.

c. RF Section

The RF Section card consists of four parts:
  • wideband RF amplifier,
  • First Mixer and Local Oscillator buffer,
  • 4-pole 92 MHz bandpass crystal filter, and
  • 92 MHz amplifier.

Wideband RF amplifier Q1 is a frequency-compensated power FET operated in common-gate mode. The low input impedance of the amplifier is transformed to approximately 50 Ohms by a broadband input transformer.

The output load impedance presented to this stage is set by a second broadband transformer through a peaking network set up to compensate for the output capacitance of the active device. THe dynamic range of the RF amplifier from sensitivity to the 1-dB-departure-from-linearity point is more than 120 dB.

The First Mixer (A1) receives signals from both the RF amplifier and the synthesizer through the Local Oscillator common base buffer (Q3). This mixer is a double-balanced (quad) mixer with a dynamic range greater than 120 dB. The Local Oscillator is balanced, and the combined signal is fed to the crystal buffer. The combination of the RF amplifier and the double-balanced mixer has a signal-handling capability of about 120 dB.

The 4-pole 92 MHz bandpass crystal filter (FL1) has a 6 dB bandwidth of about 20 KHz. This filter protects the 92 MHz IF amplifier by rejecting signals more than 10 KHz from the desired signals. Even though a strong signal more than 10 KHz away from the desired signal may be amplified by the broadband RF amplifier and be up-converted in the First Mixer, that undesired signal will be rejected by the 92 MHz filter.

The 92 MHz filter feeds the 92 MHz amplified (Q2), a dual-gate FET. This device is a low noise figure amplifier (3 dB) with delayed AGC voltage applied to the second gate. It is operated in the grounded-source configuration to provide a high input impedance to the 92 MHz filter. The 92 MHz amplifier drives a single Pi-section filter, which matches the amplifier output to the input of the Second Mixer card.

d. Second Mixer

The Second Mixer card consists of three parts:
  • A 2-pole 92 MHz crystal filter,
  • A double-balanced Second Mixer and Local Oscillator buffer combination, and
  • An 8-pole 8-KHz-wide crystal filter.

The 2-pole 92 MHz crystal filter (FL2) provides further attenuation of undesired signals more than 10 KHz away from the desired signal.

The Second Mixer is a double-balanced mixer that is fed by a Local Oscillator at 84 MHz through common-base buffer amplifier Q1.

Output of the second mixer at 8 MHz is fed to the 8-pole 8-KHz-wide crystal filter FL1. This filter is the only information filter that is used when the receiver is placed in the "WIDE" (8 KHz) bandwidth position. The output of the second mixer is transformed by L2 and C2 to the impedance required by the 8 KHz bandwidth filter. This impedance is then transformed down by L3 and C3 to the impedance required to match the 8 Mhz output.

e. 8 MHz IF Amplifier

The 8 MHz IF Amplifier consists of three parts:
  • Two IC IF amplifiers, and
  • One emitter-follower buffer amplifier.

The first IF amplifier (IC1) receives and amplifies the signal from the Second Mixer.

The output goes to the Information Filters card, where the desired bandwidth filter is selected.

The output from the Information Filters card reenters the 8 MHz IF Amplifier card
and is amplified by the second amplifier (IC2). Both of these amplifiers have AGC applied to them. The signal-handling capability of the amplifier increases for increasing ACG gain cut.

The output from the second amplifier is fed to the Detectors card and to an emitter- follower buffer on the 8 MHz IF Amplifier card. This buffer output is available on the rear panel of the receiver.

f. Information Filters

Each filter on the Information Filters card is selected by means of a diode gate, by applying 24 volts to that gate. The filters not selected are automatically shorted out by the diode gates associated with them.

When the "WIDE" (8 KHz bandwidth) pushbutton is depressed, a pad rather than a filter, is connected into the circuit. The amount of attenuation in the pad is equal to that found in one of the sideband filters. The total signal path gain is therefore constand for AM or sideband operation.

g. AM and Product Detectors.

The AM and Product Detectors card consists of four parts:
  • Product detector preamplifier,
  • Product detector,
  • AM detector preamplifier, and
  • AM detector.

The product detector and AM detector preamplifiers (IC1, IC3) are fed 8 MHz signals in parallel. Only one preamplifier, however, is used at any one time. The appropriate preamplifier is selected by ungrounding either the CW and SSB or the AM command bus. The product detector feeds the product detector (IC2), which is an IC balanced mixer. The 8 MHz BFO injection is prevented from feeding back to the 8 MHz IF strip by the reverse attenuation of the preamplifier. This prevents BFO energy from activating the ACG detector.

The AM preamplifier is similar to the product detector preamplifier, but has an input level adjustment control (R13) to equalize the audio level between AM and CW/SSB modes.

The output from the AM preamplifier feeds a diode detector whose output is combined. through an isolating resistor, with the output of the product detector and fed through a common output line to the Audio Amplifier card.

g. AGC Amplifier.

The AM and Product Detectors card consists of six parts:
  • 8 MHz AGC amplifier,
  • AGC rectifier,
  • Emitter follower,
  • IF AGC DC amplifier,
  • Delayed AGC active level shifter, and
  • Delayed AGC DC amplifier.

AGC amplifier IC1 is an IC amplifier like those used in the 8 MHz IF amplifiers, the AM detector preamplifier, and the product detector preamplifier. It provides gain to the AGC detector diodes (CR3 and CR4). The detector is followed by emitter follower Q1, which serves as a low impedance driving source for the 22 microfarad AGC decay capacitor (C9). Various resistors shunted across the decay capacitor allow variable decay times, while the emitter follower driver allows fast attack time charging to the 22 microfarad capacitor.

The decay capacitor is followed by feedback DC amplifier Q2-Q3, whose output drives the IF AGC line to the 8 MHz IF amplifier.

The IF AGC line drives active level shifter Q4-A5 with adjustable threshold. This level shifter drives another DC amplifier pair (Q6-Q7) and provides the delayed AGC voltage to the AGC gate of the 92 MHz IF amplifier in the RF Section card. The adjustable threshold serves to determine the AGC voltage point at which the 92 MHz IF amplifier begins to cut gain. This delaying of AGC voltage to the 92 MHz IF amplifier is necesary to ensure that the signal-to-noise ratio is not degraded with AGC action at medium input signal levels, where noise figure degradation in the front end must be avoided. AGC action to the 92 MHz IF amplifier acts in a reverse direction from the 8 MHz IF amplifier, in that gain is decreased as the AGC voltage falls below 8.2 volts.

j. Variable BFO

The variable BFO consists of an 8 MHz Colpitts crystal oscillator (Q1), followed by an emitter follower buffer stage (Q2). A switch built into the BFO RF-tight (shielded) compartment switches between the output of this variable BFO and the fixed 8 MHz output (derived from the 8 MHz low-frequency standard), and passes the signal on to the product detector. In the AM mode, the +28 Volt DC supply voltage to the variable BFO is disabled. THe crystal oscillator frequency is pulled by means of variable capacitor C4 in the BFO compartment.


a. Block Diagram Analysis

The synthesizer in the ITT Mackay Marine Type 3020 Radio Receiver consists of two programmable phase locked loops. The Minor Loop is controlled by the 100 Hz, 1 KHz, and the 10 KHz positions of the front panel frequency select switches. The Major Loop is controlled by both the output of the Minor Loop and the settings of the 100 KHz, 1 MHz, and 10 MHz frequency select switches.

Both the Major and Minor Loops are phase-locked to an 8 MHz temperature compensated crystal oscillator (TCXO) standard, although in the interface between the two loops a conversion oscillator (84 MHz) is used that is not phase locked to the standard. Since this 84 MHz signal provides the injection to the Second Mixer in the receiver signal path, and since the output of the synthesizer provides the injection to the First Mixer in the signal path, the overall receiver becomes drift cancelled. That is, any shift in the 84 MHz oscillator away from 84 MHz is compensated for in the system on a cycle-for-cycle basis. (insert simplified graphic showing first mixer with 10 MHz RF input and 102 MHz

First LO input, 92 MHz output to 92 MHz filter, and Second Mixer with 92 MHz input from filter and 84 MHz input from Second LO, yielding 8 MHz output from Second Mixer)

If the Second LO frequency happens to be 84.002 MHz, then the first LO becomes 102.002 MHz.

The conversion then becomes 10.0 MHz to 92.002 MHz, and 92.002 MHz back to 8.002 MHz. The receiver has thus compensated for the slight change in the 84 MHz frequency and will do so as long as the signal remains within the +/- 10KHz passband of the 92 MHz First IF filters.

The Minor Loop produces 999 steps from 70.400 to 71.9984 MHz at its output. THe output frequency is mixes with a 64 MHz signal phase locked to the 8 MHz Low Frequency Reference crystal standard to yield a range from 6.400 to 7.9984 MHz. (The 64 MHz crystal oscillator may be taken out of phase lock mode and allowed to run free. The frequency then can be pulled to provide fine tuning.) This output is divided by a divisor ratio from 4000 to 4999 to yield a 1.6 KHz output. This 1.6 KHz output is compared in a phase detector to a 1.6 KHz signal derived from the 8 MHz Low Frequency Reference crystal standard. If a difference is present between the output from the variable divider and the 1.6 KHz reference, the loop adjusts the frequency until no difference is present. For example, suppose a dial setting of the frequency select switches is chosen and the divider ratio is 4100. The VCO will adjust itself until

(X-64000 KHz) / 4100 = 1.6 KHz, where X = 70560 KHz (70.560 MHz).

The Major Loop produces, for any particular Minor Loop output frequency, 30 steps in its output. The output of the Major Loop varies from 92.0000 to 121.0000 MHz. With a 92.0000 MHz First IF, this yields a receiver frequency range from 0 to 29.9999 MHz.

The Major Loop takes the 70.4 to 71.9984 MHz output from the Minor Loop and first divides it by 16 to yield a rance from 4.0 to 4.9999 MHz. This range of frequencies is then mixed with the output of an 84 MHz crystal oscillator, discussed above, to yield a range from 88.4 to 88.4999 MHz. This range is then used to miz with the output range of the Major Loop, this producing a range from 3.6 to 33.500 MHz.

This 3.6 to 33.500 MHz range is fed to a variable divider, which divides by 2 and then by 36 to 335. If the loop is at the correct output frequency, the final result of these operations is an output from the variable divider at 50 KHz, the sampling frequency of the Major Loop. The output of the variable dividor is compared to a 50 KHz pulse train derived from the 8 MHz Low Frequency Reference crystal standard.

For example, if the Minor Loop output frequency is 70.560 MHz, as in the previous example, division by 16 yields (70.560/16) = 4.410 MHz. This is mixed with 84.0 MHz to yield 88.410 MHz. If the variable divider is programmed to divide by 100 (/2; /50), then the output frequency will be (X - 88410 KHz)/100 = = 50 KHz, and X then must be 93410 KHz (93.410 MHz).

Therefore 93.410 MHz - 92.000 MHz IF - 1.410 MHz desired reception frequency.

b. Low Frequency Reference

The purpose of the Low Frequency Reference is to provide 1.6 KHz, 50 KHz, and 8 MHz reference pulses for the Minor Loop, Major Loop, and the VHF Reference, respectively. An 8 MHz output also is provided.

The output from TCXO Y1 is buffered in Q1 and fed to the 8 MHz product detector. It also is buffered by Q2 and Q3 and fed into a digital buffer the inverters in ICA) at TTL level to feed the VHF Reference Card.

IC1 and IC2 divide the 8 MHz reference by 10 and then by 150 to produce a 50 KHz output. A 1.25-microsecond-wide pulse at a 50 KHz rate is provided from gate B decoding from IC2. A positive rising and negative falling pulse is provided for the Major Loop phase detector at 50 KHz.

The 800 KHz output from IC1 is fed to IC3, then Ic4, and IC5, which form a divide-by-500. This yields a 1.6 KHz output frequency. Gates C and A decode the various dividers to provide a 12.5-microsecond-wide output pulse at a rate if 1.6 KHz. A positive rising and negative falling ourpur pulse are provided to the Minor Loop phase detector at 1.6 KHz.

c. VHF Reference Card

The purpose of the VHF Reference Card is to provide an 84 MHz output signal for the Loop Translator and signal path Second Mixer, and to provide a 64 MHz output that is phase locked to the 8 MHz standard for the Minor Loop Analog card.

The VHF Reference Card contains five parts:
  • An 84 MHz crystal oscillator and buffer,
  • a 64 MHz crystal oscillator,
  • an analog-to-ECL (Emitter Coupled Logic) level 64 MHz buffer,
  • an ECL divide-by-8, and
  • a phase detector DC control system for the 64 MHz phase locked loop.

The 84 MHz oscillator (Q1) is a modified Colpitts crystal oscillator fed into a FET buffer (Q2) and then to the signal path.

The 64 MHz oscillator (Q3) is another modified Colpitts crystal oscillator, but one whose frequency is pullable by means of varactor diode CR1. The 64 MHz oscillator can be phase locked to the 8 MHz standard, or can be allowed to run free. Voltage applied to CR1 can be used to fine-tune the receiver.

In the phase lock mode, the 64 MHz oscillator is followed by buffer Q4-Q5, which converts the analog 64 MHz signals to emitter-coupled logic (ECL) levels to drive the ECL high-speed divide-by-8 counter composed of IC4 and IC5. This divide-by-8 produces 8 MHz pulses that are fed to low-pass filter C40, L8, and C41.

The filtered 8 MHz is then fed to the phase detector DC control system, IC3, which is a cascode mixer type phase detector. The 8 MHz energy from the Low Frequency Reference also is fed to IC3. The DC output from IC3 goes to varactor CR1 through the fine-tune-enable relay to complete the loop.

d. Minor Loop Analog

The Minor Loop Analog card consists of four parts:
  • The Minor Loop offset mixer and 66 MHz buffer,
  • the 70.4 to 71.9984 MHz VCO (Voltage Controlled Oscillator) and buffer,
  • the Minor Loop sample-and-hold phase detector, and
  • the loop filter / 1.6 KHz T-notch filter.

The Minor Loop offset mixer is an IC cascode mixer, IC2, which is fed 64 MHz Local Oscillator energy through the 64 MHz buffer, Q11, which in turn is fed from the VHF Reference Card. The buffered output of the 70.4 to 71.9984 MHz VCO (buffered by IC3) also is fed to the mixer, and the 6.4 to 7.9984 difference output from the offset mixer is fed to the Minor Loop Variable Divider.

The VCO is a form of Hartley oscillator. The frequency can be changed by varying the voltage across varactor diodes CR4 and CR5. IC3, a cascode amplifier, buffers the VCO and feeds 70.4 to 71.9984 MHz energy to the divide-by-16 on the Loop Translator card and to the Minor Loop offset mixer.

The Minor Loop sample-and-hold phase detector system consists of Q1 through Q7.

Ramp capacitor C15 is charged by constant current generator Q2, and is discharged by ramp switch Q1 triggered by the 1.6 KHz reference pulse. During the rise of the ramp voltage the output from the Minor Loop Variable Divider pulses on sampler gate Q6 and Q7 for a short period. At this time energy is transferred from the sampler driver system Q3, Q4, and Q5 to sample capacitor C18.

The DC amplifier composed of Q8, Q12, and Q9 amplifies the voltage across the sampler capacitor and applies it to the loop filter (R4, R5, and C3), and then to the 1.6 KHz T-notch filter R36, R38, C20, C21, and C22. The filtered DC then is applied to varactors CR4 and CR5.

The principle of this phase lock system is that if successive voltage samples are not the same, then the frequency is wrong and must be changed in the loop until successive samples are the same.

Diodes CR7 and CR8 serve to short the loop and notch filters for large voltage swings and thus serve to reduce the time to achieve acquisition and phase lock.

e. Minor Loop Variable Divider